Solid State Refrigeration and Microchips

This gives us another eyeball into the world of thin film solid state refrigeration. Everyone understands the importance of this work and here we see application work underway to harness this for microchip cooling.

We are very much on the early phases of the research road, but the destination is clear and obvious. We need solid state hyper cold surfaces to maintain super conductor circuits and perhaps magnetic exclusion. I think it is fair to say that everyone is going in the same direction.

As I have posted, we know this will give us the ability to manufacture a closed craft able to exclude the surrounding magnetic field. This still a very small step.

http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1599508
Solid-state refrigeration for cooling microprocessors
Ramanathan, S. Chrysler, G.M.
Components Res. Dept., Intel Corp., Hillsboro, USA;
This paper appears in:

Components and Packaging Technologies, IEEE Transactions on
Publication Date: March 2006
Volume: 29, Issue: 1
On page(s): 179- 183
ISSN: 1521-3331
INSPEC Accession Number: 8808104
Digital Object Identifier: 10.1109/TCAPT.2006.
Current Version Published: 2006-02-27

Abstract

Thin-film thermoelectrics (TECs) are potential candidates for cooling microprocessors due to their large cooling power density and ability to integrate with packages. In addition, there are no moving parts or noise generated during their operation. In particular, thin-film TECs offer the ability to cool localized regions of high heat flux (hot spots) in the die selectively, which is very useful for chips with nonuniform power maps. In this paper, we theoretically analyze the performance of thin-film TECs for reducing the junction temperature at hot spots in a die. We report the reduction in junction temperature for a representative power map as a function of input power to the TEC films for the first time. The potential benefits and limitations of scaling the TEC legs are calculated by solving the general TEC equations within a fully three-dimensional numerical model of the assembled die and package. Parasitic electrical contact resistance and back conduction from the hot-side to cold-side through any encapsulating or material surrounding TEC legs are also included in the model. Model calculations are performed for TEC figure of merit (ZT) values of 1 and 3 (for comparison). We determine an operating envelope for the TECs that leads to an optimum cooling capability. The impact of operating the TECs are calculated as well taking into account the temperature increase of the heat spreader due to heat influx from the hot-side of the TEC. It is shown that material breakthroughs as well as process improvements could enable solid-state refrigeration to be an attractive candidate for spot cooling in microprocessors.